﻿/**
 * @file		dd_pmc_hdmac.h
 * @brief		PMC HDMAC driver
 * @note		None
 * @attention	None
 * 
 * <B><I>Copyright 2016 Socionext Inc.</I></B>
 */

/** @weakgroup dd_pmc_hdmac_overview
@{
	CM0 PMC - HDMAC Driver.<br>
	<br>
	The number of channels is 8 (ch0 - ch7).<br>
	The peripheral macro that is capable of starting DMA transfer is as follows:
	<table>
		<tr>
			<th>HDMAC ch</th>
			<th>Peripheral Macro</th>
		</tr>
		<tr>
			<td>0</td>
			<td>ADC interrupt</td>
		</tr>
		<tr>
			<td>1</td>
			<td>UART Reception end interrupt</td>
		</tr>
		<tr>
			<td>2</td>
			<td>UART Transmission end interrup</td>
		</tr>
		<tr>
			<td>3</td>
			<td>SPI Transmission end request</td>
		</tr>
		<tr>
			<td>4</td>
			<td>SPI Reception end request</td>
		</tr>
		<tr>
			<td>5</td>
			<td>none</td>
		</tr>
		<tr>
			<td>6</td>
			<td>none</td>
		</tr>
		<tr>
			<td>7</td>
			<td>none</td>
		</tr>
	</table><br>
	The request to each DMA channel is connected as shown below.<br>
	- @ref HDMAC_DREQ
	- @ref HDMAC_IDREQ
	@section HDMAC_DREQ	Connection of DREQ
	<table>
		<tr>
			<th>DREQ(HDMAC ch)</th>
			<th>HDMAC Start factor</th>
		</tr>
		<tr>
			<td>0</td>
			<td>none</td>
		</tr>
		<tr>
			<td>1</td>
			<td>none</td>
		</tr>
		<tr>
			<td>2</td>
			<td>none</td>
		</tr>
		<tr>
			<td>3</td>
			<td>none</td>
		</tr>
		<tr>
			<td>4</td>
			<td>none</td>
		</tr>
		<tr>
			<td>5</td>
			<td>none</td>
		</tr>
		<tr>
			<td>6</td>
			<td>none</td>
		</tr>
		<tr>
			<td>7</td>
			<td>none</td>
		</tr>
	</table>
	@section HDMAC_IDREQ	Connection of IDREQ
	<table>
		<tr>
			<th>IDREQ</th>
			<th>HDMAC Start factor</th>
		</tr>
		<tr>
			<td>0</td>
			<td>ADC DMA request</td>
		</tr>
		<tr>
			<td>1</td>
			<td>UART reception end</td>
		</tr>
		<tr>
			<td>2</td>
			<td>UART transmission end</td>
		</tr>
		<tr>
			<td>3</td>
			<td>SPI transmission end request</td>
		</tr>
		<tr>
			<td>4</td>
			<td>SPI reception end request</td>
		</tr>
		<tr>
			<td>5</td>
			<td>none</td>
		</tr>
		<tr>
			<td>6</td>
			<td>none</td>
		</tr>
		<tr>
			<td>7</td>
			<td>none</td>
		</tr>
		<tr>
			<td>8</td>
			<td>none</td>
		</tr>
		<tr>
			<td>9</td>
			<td>none</td>
		</tr>
		<tr>
			<td>10</td>
			<td>none</td>
		</tr>
		<tr>
			<td>11</td>
			<td>none</td>
		</tr>
		<tr>
			<td>12</td>
			<td>none</td>
		</tr>
		<tr>
			<td>13</td>
			<td>none</td>
		</tr>
		<tr>
			<td>14</td>
			<td>none</td>
		</tr>
		<tr>
			<td>15</td>
			<td>none</td>
		</tr>
	</table>
@}*//* --- end of dd_pmc_hdmac_overview */

/** @weakgroup dd_pmc_hdmac_sequence
@{
	- @ref HDMAC_Async
	- @ref HDMAC_Async_Sample
	@section HDMAC_Async	Sequence of HDMAC forwarding sequence
	@image html dd_pmc_hdmac_async.png
	<br>
	@section HDMAC_Async_Sample		Sample of HDMAC (Async)
	The example of executing Asynchronous processing is as follows.
	@code
	INT32                 ret;
	UINT32                wait_mode;
	USHORT                status = 0;
	UCHAR                 ch;
	T_DD_PMC_HDMAC_CTRL_TRNS HDMAC_ctrl_trns;

	ch = 0;

	HDMAC_ctrl_trns.mode.input_sel   = D_DD_PMC_HDMAC_IS_SOFT;
	HDMAC_ctrl_trns.mode.mode_sel    = D_DD_PMC_HDMAC_MS_BLK;
	HDMAC_ctrl_trns.mode.src_fix     = D_DD_PMC_HDMAC_FS_INCR;
	HDMAC_ctrl_trns.mode.dst_fix     = D_DD_PMC_HDMAC_FD_INCR;
	HDMAC_ctrl_trns.mode.beat_type   = D_DD_PMC_HDMAC_BT_NORMAL;

	HDMAC_ctrl_trns.size.trns_width  = D_DD_PMC_HDMAC_TW_WORD;
	HDMAC_ctrl_trns.size.trns_size   = TRANS_SIZE;
	HDMAC_ctrl_trns.size.src_addr    = SRC_TOP_ADDR;
	HDMAC_ctrl_trns.size.dst_addr    = DST_TOP_ADDR;

	HDMAC_ctrl_trns.int_handler      = sample_dma_callback;

	while (1) {
		ret = Dd_PMC_HDMAC_Ctrl_Trns(ch, &HDMAC_ctrl_trns);
		if (ret != 0) {
			// ERROR
			break;
		}
		ret = Dd_PMC_HDMAC_Start_Async(ch);
		if (ret != 0) {
			// ERROR
			break;
		}
		break;
	}
	@endcode

@}*//* --- end of dd_pmc_hdmac_sequence */

#ifndef _DD_PMC_HDMAC_H_
#define _DD_PMC_HDMAC_H_

/** @weakgroup dd_pmc_hdmac_definition
@{*/

#include "driver_common.h"

/*----------------------------------------------------------------------*/
/* Definition															*/
/*----------------------------------------------------------------------*/
//---------------------- driver  section -------------------------------
// Interrupt flag
#define	D_DD_PMC_HDMAC_FLG_CH0				(0x00000001)								/**< Event flag of channel 0 */
#define	D_DD_PMC_HDMAC_FLG_CH1				(0x00000002)								/**< Event flag of channel 1 */
#define	D_DD_PMC_HDMAC_FLG_CH2				(0x00000004)								/**< Event flag of channel 2 */
#define	D_DD_PMC_HDMAC_FLG_CH3				(0x00000008)								/**< Event flag of channel 3 */
#define	D_DD_PMC_HDMAC_FLG_CH4				(0x00000010)								/**< Event flag of channel 4 */
#define	D_DD_PMC_HDMAC_FLG_CH5				(0x00000020)								/**< Event flag of channel 5 */
#define	D_DD_PMC_HDMAC_FLG_CH6				(0x00000040)								/**< Event flag of channel 6 */
#define	D_DD_PMC_HDMAC_FLG_CH7				(0x00000080)								/**< Event flag of channel 7 */

// Num of channel
#define D_DD_PMC_HDMAC_CH_NUM_MAX			(8)											/**< The maximum values of number of channels */

// Return value of HDMAC processing result
#define	D_DD_PMC_HDMAC_SYSTEM_ERR			(D_DD_PMC_HDMAC | D_DDIM_SYSTEM_ERROR)		/**< System Error */
#define	D_DD_PMC_HDMAC_INPUT_PARAM_ERR		(D_DD_PMC_HDMAC | D_DDIM_INPUT_PARAM_ERROR)	/**< Input Parameter Error */
#define	D_DD_PMC_HDMAC_TIMEOUT_ERR			(D_DD_PMC_HDMAC | D_DDIM_TIMEOUT)			/**< Time Out */
#define	D_DD_PMC_HDMAC_EXC_LOCK_NG			(D_DD_PMC_HDMAC | D_DDIM_EXT_LOCK_NG)		/**< Exclusive control NG */
#define	D_DD_PMC_HDMAC_BUSY_ERR				(D_DD_PMC_HDMAC | D_DDIM_MACRO_BUSY_NG)		/**< HDMAC Busy */
#define	D_DD_PMC_HDMAC_SEM_NG				(D_DD_PMC_HDMAC | D_DDIM_SEM_NG)			/**< HDMAC Semaphore acquisition NG */
#define	D_DD_PMC_HDMAC_SEM_TIMEOUT			(D_DD_PMC_HDMAC | D_DDIM_SEM_TIMEOUT)		/**< HDMAC Semaphore acquisition Time Out */

// HDMAC exclusion mode
#define D_DD_PMC_HDMAC_EXC_OFF				(0)											/**< Exclusive control release */
#define D_DD_PMC_HDMAC_EXC_ON				(1)											/**< Exclusive control setting */

/*** Value of setting DMACA register ***/
// Input Select(IS)
#define D_DD_PMC_HDMAC_IS_SOFT				(0x00)										/**< Software */
#define D_DD_PMC_HDMAC_IS_DREQ_H			(0x01)										/**< DREQ High level or Positive edge */
#define D_DD_PMC_HDMAC_IS_DREQ_L			(0x02)										/**< DREQ Low level or Negative edge */
#define D_DD_PMC_HDMAC_IS_IDREQ_0			(0x10)										/**< IDREQ[0] High level or Positive edge (for ADC DMA request) */
#define D_DD_PMC_HDMAC_IS_IDREQ_1			(0x11)										/**< IDREQ[1] High level or Positive edge (for UART reception end) */
#define D_DD_PMC_HDMAC_IS_IDREQ_2			(0x12)										/**< IDREQ[2] High level or Positive edge (for UART transmission end) */
#define D_DD_PMC_HDMAC_IS_IDREQ_3			(0x13)										/**< IDREQ[3] High level or Positive edge (for SPI transmission end request) */
#define D_DD_PMC_HDMAC_IS_IDREQ_4			(0x14)										/**< IDREQ[4] High level or Positive edge (for SPI reception end request) */
#define D_DD_PMC_HDMAC_IS_IDREQ_5			(0x15)										/**< IDREQ[5] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_6			(0x16)										/**< IDREQ[6] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_7			(0x17)										/**< IDREQ[7] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_8			(0x18)										/**< IDREQ[8] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_9			(0x19)										/**< IDREQ[9] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_10			(0x1A)										/**< IDREQ[10] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_11			(0x1B)										/**< IDREQ[11] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_12			(0x1C)										/**< IDREQ[12] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_13			(0x1D)										/**< IDREQ[13] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_14			(0x1E)										/**< IDREQ[14] High level or Positive edge (reserved) */
#define D_DD_PMC_HDMAC_IS_IDREQ_15			(0x1F)										/**< IDREQ[15] High level or Positive edge (reserved) */


// Beat Type(BT)
#define D_DD_PMC_HDMAC_BT_NORMAL			(0x00)										/**< NORMAL (same as SINGLE) */
#define D_DD_PMC_HDMAC_BT_SINGLE			(0x08)										/**< SINGLE (same as NORMAL) */
#define D_DD_PMC_HDMAC_BT_INCR				(0x09)										/**< INCR */
#define D_DD_PMC_HDMAC_BT_WRAP4				(0x0A)										/**< WRAP4 */
#define D_DD_PMC_HDMAC_BT_INCR4				(0x0B)										/**< INCR4 */
#define D_DD_PMC_HDMAC_BT_WRAP8				(0x0C)										/**< WRAP8 */
#define D_DD_PMC_HDMAC_BT_INCR8				(0x0D)										/**< INCR8 */
#define D_DD_PMC_HDMAC_BT_WRAP16			(0x0E)										/**< WRAP16 */
#define D_DD_PMC_HDMAC_BT_INCR16			(0x0F)										/**< INCR16 */

/*** Value of setting DMACB register ***/
// Mode Select(MS)
#define D_DD_PMC_HDMAC_MS_BLK				(0x00)										/**< Block Transfer mode */
#define D_DD_PMC_HDMAC_MS_BURST				(0x01)										/**< Burst Transfer mode */
#define D_DD_PMC_HDMAC_MS_DEMAND			(0x02)										/**< Demand Transfer mode */

// Transfer Width(TW)
#define D_DD_PMC_HDMAC_TW_BYTE				(0x00)										/**< Byte */
#define D_DD_PMC_HDMAC_TW_HWORD				(0x01)										/**< Half-Word */
#define D_DD_PMC_HDMAC_TW_WORD				(0x02)										/**< Word */

// Fixed Source(FS)
#define D_DD_PMC_HDMAC_FS_INCR				(0x00)										/**< Source address is incremented */
#define D_DD_PMC_HDMAC_FS_FIX				(0x01)										/**< Source address is fixed */

// Fixed Destination(FD)
#define D_DD_PMC_HDMAC_FD_INCR				(0x00)										/**< Destination address is incremented */
#define D_DD_PMC_HDMAC_FD_FIX				(0x01)										/**< Destination address is fixed */

// Reload Count(RC)
#define D_DD_PMC_HDMAC_RC_DISABLE			(0x00)										/**< Reload function of the transfer count is disabled */
#define D_DD_PMC_HDMAC_RC_ENABLE			(0x01)										/**< Reload function of the transfer count is enabled */

// Reload Source(RS)
#define D_DD_PMC_HDMAC_RS_DISABLE			(0x00)										/**< Reload function of the source address is disabled */
#define D_DD_PMC_HDMAC_RS_ENABLE			(0x01)										/**< Reload function of the source address is enabled */

// Reload Destination(RD)
#define D_DD_PMC_HDMAC_RD_DISABLE			(0x00)										/**< Reload function of the destination address is disabled */
#define D_DD_PMC_HDMAC_RD_ENABLE			(0x01)										/**< Reload function of the destination address is enabled */

// Stop Status(SS)
#define D_DD_PMC_HDMAC_SS_NONE				(0x00)										/**< Initial value */
#define D_DD_PMC_HDMAC_SS_ADDR_OVER			(0x01)										/**< Address overflow (Error) */
#define D_DD_PMC_HDMAC_SS_STOP_REQ			(0x02)										/**< Transfer stop request (Error) */
#define D_DD_PMC_HDMAC_SS_SRC_ERR			(0x03)										/**< Source access error (Error) */
#define D_DD_PMC_HDMAC_SS_DST_ERR			(0x04)										/**< Destination access error (Error) */
#define D_DD_PMC_HDMAC_SS_NORMAL_END		(0x05)										/**< Normal end */
#define D_DD_PMC_HDMAC_SS_PAUSE				(0x07)										/**< HDMAC pause */

// Arbitration mode
#define D_DD_PMC_HDMAC_ARB_FIX				(0x00)										/**< priority fixed */
#define D_DD_PMC_HDMAC_ARB_ROTATE			(0x01)										/**< priority rotated */

#ifdef CO_DDIM_UTILITY_USE
//---------------------- utility section -------------------------------
//---------------------- colabo  section -------------------------------
#endif

/*----------------------------------------------------------------------*/
/* Enumeration															*/
/*----------------------------------------------------------------------*/
// Nothing Special
//---------------------- driver  section -------------------------------

#ifdef CO_DDIM_UTILITY_USE
//---------------------- utility section -------------------------------
//---------------------- colabo  section -------------------------------
#endif

/*----------------------------------------------------------------------*/
/* Structure  															*/
/*----------------------------------------------------------------------*/
//---------------------- driver  section -------------------------------
/** HDMAC Control DMACA */
typedef union {
	ULONG		word;						/**< for ULONG access */
	struct {
		ULONG	tc				:16;		/**< Transfer Count (16'h0000 to 16'hFFFF) */
		ULONG	bc				:4;			/**< Block Count (4'b0000 to 4'bFFFF)<br>
												 In the demand transfer mode, BC must be set to 4'b0000. */
		ULONG	bt				:4;			/**< Beat Type (4'b0000, 4'b1000 to 4'b1111)<br>
												 In the demand transfer mode, incrementing/wrapping burst (INCR*, WRAP*) is not supported. */
		ULONG	is				:5;			/**< Input Select (5'b00000, 5'b01110 to 5'b11111) */
		ULONG					:3;			/**< Reserved */
	} bit;									/**< for bit access */
} U_DD_PMC_HDMAC_DMACA;

/** HDMAC Control DMACB */
typedef union {
	ULONG		word;						/**< for ULONG access */
	struct {
		ULONG					:8;			/**< Reserved */
		ULONG	dp				:4;			/**< Destination Protection (4'b0000 to 4'b1111) */
		ULONG	sp				:4;			/**< Source Protection (4'b0000 to 4'b1111) */
		ULONG	ss				:3;			/**< Stop Status (3'b000 to 3'b111) */
		ULONG	ci				:1;			/**< Completion Interrupt (0 or 1) */
		ULONG	ei				:1;			/**< Error Interrupt (0 or 1) */
		ULONG	rd				:1;			/**< Reload Destination (0 or 1) */
		ULONG	rs				:1;			/**< Reload Source (0 or 1) */
		ULONG	rc				:1;			/**< Reload Count (0 or 1) */
		ULONG	fd				:1;			/**< Fixed Destination (0 or 1) */
		ULONG	fs				:1;			/**< Fixed Source (0 or 1) */
		ULONG	tw				:2;			/**< Transfer Width (2'b00 to 2'b10) */
		ULONG	ms				:2;			/**< Mode Select (2'b00 to 2'b10) */
		ULONG	tt				:2;			/**< Transfer Type (2'b00) */
	} bit;									/**< for bit access */
} U_DD_PMC_HDMAC_DMACB;


/** HDMAC Control Common */
typedef struct {
	U_DD_PMC_HDMAC_DMACA	config_a;		/**< Configuration A */
	U_DD_PMC_HDMAC_DMACB	config_b;		/**< Configuration B */
	ULONG					src_addr;		/**< Source Address */
	ULONG					dst_addr;		/**< Destination Address */
} T_DD_PMC_HDMAC_CTRL;


/** HDMAC Transfer mode */
typedef struct {
	UCHAR					input_sel;		/**< Input Select (5'b00000, 5'b01110 to 5'b11111) */
	UCHAR					mode_sel;		/**< Mode Select (2'b00 to 2'b10) */
	UCHAR					src_fix;		/**< Source Address fixed (0 or 1) */
	UCHAR					dst_fix;		/**< Destination Address fixed (0 or 1) */
	UCHAR					beat_type;		/**< Beat Type (4'b0000, 4'b1000 to 4'b1111)<br>
												 In the demand transfer mode, incrementing/wrapping burst (INCR*, WRAP*) is not supported. */
} T_DD_PMC_HDMAC_TRNS_MODE;

/** HDMAC Transfer size */
typedef struct {
	UCHAR					trns_width;		/**< Transfer Width (2'b00 to 2'b10) */
	ULONG					trns_size;		/**< Transfer Size */
	ULONG					src_addr;		/**< Source Address */
	ULONG					dst_addr;		/**< Destination Address */
} T_DD_PMC_HDMAC_TRNS_SIZE;

/** HDMAC Transfer Control */
typedef struct {
	T_DD_PMC_HDMAC_TRNS_MODE	mode;		/**< Transfer mode set */
	T_DD_PMC_HDMAC_TRNS_SIZE	size;		/**< Transfer size set */
} T_DD_PMC_HDMAC_CTRL_TRNS;

/** HDMAC Reload mode set */
typedef struct {
	UCHAR					reload_cnt;		/**< Reload Count mode (0 or 1) */
	UCHAR					reload_src;		/**< Reload Source mode (0 or 1) */
	UCHAR					reload_dst;		/**< Reload Destination mode (0 or 1) */
} T_DD_PMC_HDMAC_RELOAD_MODE;


#ifdef CO_DDIM_UTILITY_USE
//---------------------- utility section -------------------------------

//---------------------- colabo  section -------------------------------
#endif

/*----------------------------------------------------------------------*/
/* Grobal Data															*/
/*----------------------------------------------------------------------*/
// Nothing Special

/*----------------------------------------------------------------------*/
/* Macro																*/
/*----------------------------------------------------------------------*/
// Nothing Special

/* @} */	// dd_pmc_hdmac_definition group

/** @weakgroup dd_pmc_hdmac_api
@{*/
/*----------------------------------------------------------------------*/
/* Function																*/
/*----------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif

//---------------------- driver  section -------------------------------
/**
The member who exists in the structure of "T_DD_PMC_HDMAC_CTRL" is set.<br>

@param [in] ch				Channel number (0 to 7)
@param [in] HDMAC_ctrl		HDMAC control data. See @ref T_DD_PMC_HDMAC_CTRL
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
@retval D_DD_PMC_HDMAC_BUSY_ERR			HDMAC is being forwarded. 
@remarks In the case of synchronous mode, please don't setting "int_handler". (It ignores, even if it has setting)<br>
         In the case of the asynchronous mode, an end can be supervised by calling "Dd_PMC_HDMAC_Wait_End()" or setting up "intHandler".<br>
         When you don't call "Dd_PMC_HDMAC_Wait_End()", please be sure to set up "int_handler".
*/
extern	INT32	Dd_PMC_HDMAC_Ctrl_Common( UCHAR ch, T_DD_PMC_HDMAC_CTRL const *const HDMAC_ctrl );

/**
The member who exists in the structure of "T_DD_PMC_HDMAC_CTRL_TRNS" is set.<br>

@param [in] ch					Channel number (0 to 7)
@param [in] HDMAC_ctrl_trans	HDMAC control data. See @ref T_DD_PMC_HDMAC_CTRL_TRNS
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
@retval D_DD_PMC_HDMAC_BUSY_ERR			HDMAC is being forwarded. 
@remarks In the case of synchronous mode, please don't setting "int_handler". (It ignores, even if it has setting)<br>
         In the case of the asynchronous mode, an end can be supervised by calling "DD_PMC_HDMAC_Wait_End()" or setting up "intHandler".<br>
         When you don't call "Dd_PMC_HDMAC_Wait_End()", please be sure to set up "int_handler".<br>
         <br>
         Transfer MAX size of this API as following.<br>
          - Block Transfer mode and Burst Transfer mode<br>
         	WORD transfer (source address and destination address are 4byte alignment) : MAX size is 4MByte.<br>
         	HALF WORD transfer (source address and destination address are 2byte alignment) : MAX size is 2MByte.<br>
         	BYTE transfer (source address and destination address are 1byte alignment) : MAX size is 1MByte.<br>
          - Demand Transfer mode<br>
         	WORD transfer (source address and destination address are 4byte alignment) : MAX size is 256KByte.<br>
         	HALF WORD transfer (source address and destination address are 2byte alignment) : MAX size is 128KByte.<br>
         	BYTE transfer (source address and destination address are 1byte alignment) : MAX size is 64KByte.<br>
*/
extern	INT32	Dd_PMC_HDMAC_Ctrl_Trns( UCHAR ch, T_DD_PMC_HDMAC_CTRL_TRNS const *const HDMAC_ctrl_trans );

/**
The member who exists in the structure of "T_DD_PMC_HDMAC_TRNS_SIZE" is set.<br>

@param [in] ch					Channel number (0 to 7)
@param [in] HDMAC_trns_size	HDMAC transfer size data. See @ref T_DD_PMC_HDMAC_TRNS_SIZE
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
@retval D_DD_PMC_HDMAC_BUSY_ERR			HDMAC is being forwarded. 
@remarks 
         Please call the Dd_PMC_HDMAC_Ctrl_Common or Dd_PMC_HDMAC_Ctrl_Trns before this API.<br>
         Transfer MAX size of this API as following.<br>
          - Block Transfer mode and Burst Transfer mode<br>
         	WORD transfer (source address and destination address are 4byte alignment) : MAX size is 4MByte.<br>
         	HALF WORD transfer (source address and destination address are 2byte alignment) : MAX size is 2MByte.<br>
         	BYTE transfer (source address and destination address are 1byte alignment) : MAX size is 1MByte.<br>
          - Demand Transfer mode<br>
         	WORD transfer (source address and destination address are 4byte alignment) : MAX size is 256KByte.<br>
         	HALF WORD transfer (source address and destination address are 2byte alignment) : MAX size is 128KByte.<br>
         	BYTE transfer (source address and destination address are 1byte alignment) : MAX size is 64KByte.<br>
*/
extern	INT32	Dd_PMC_HDMAC_Set_Trns_Size( UCHAR ch, T_DD_PMC_HDMAC_TRNS_SIZE const *const HDMAC_trns_size );

/**
HDMAC start of "Asynchronous" mode.<br>
The operation of HDMAC of specified ch begins.

@param [in] ch				Channel number (0 to 7)
@param [in] *intHandler	Pointer of callback function
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
@remarks When this mode is used, the CALLBACK function is registered or Dd_PMC_HDMAC_Wait_End() API please call,
         so check the HDMAC forwarding completion.
*/
extern	INT32	Dd_PMC_HDMAC_Start_Async( UCHAR ch, VP_CALLBACK intHandler );

/**
The operation of HDMAC of specified ch is stopped.

@param [in] ch				Channel number (0 to 7)
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Stop( UCHAR ch );

/**
The operation of HDMAC of specified ch is paused.

@param [in] ch				Channel number (0 to 7)
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Pause( UCHAR ch );

/**
The operation of HDMAC of specified ch is resumed.

@param [in] ch				Channel number (0 to 7)
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Resume( UCHAR ch );

/**
The status bit of the DMACB register is cleared.

@param [in] ch				Channel number (0 to 7)
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Clear_Status( UCHAR ch );

/**
The content of the DMACB register is acquired.

@param [in] ch				Channel number (0 to 7)
@param [out] *status		Channel Status Register pointer
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Get_Status( UCHAR ch, USHORT *const status );

/**
The value of the transferd size of the specified channel is acquired.

@param [in] ch				Channel number (0 to 7)
@retval size							transferd size of the specified channel
@remarks This API forced cancel exclusive control if process is under executing.
*/
extern	ULONG	Dd_PMC_HDMAC_Get_Trns_Size( UCHAR ch );


/**
The value of the remainder transfer size of the specified channel is acquired.

@param [in] ch				Channel number (0 to 7)
@retval size							remainder transfer size of the specified channel
@remarks This API forced cancel exclusive control if process is under executing.
*/
extern	ULONG	Dd_PMC_HDMAC_Get_Remain_Trns_Size( UCHAR ch );


/**
The value of the total transfer size of the specified channel is acquired.

@param [in] ch				Channel number (0 to 7)
@retval size							total transfer size of the specified channel
*/
extern	ULONG	Dd_PMC_HDMAC_Get_Total_Trns_Size( UCHAR ch );

/**
set the source address (DMACSA) of the specified channel is acquired.

@param [in] ch				Channel number (0 to 7)
@param [in] src_addr		Source address of the specified channel
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Set_Src_Addr( UCHAR ch, ULONG src_addr );

/**
The value of the source address (DMACSA) of the specified channel is acquired.

@param [in] ch				Channel number (0 to 7)
@retval src_addr						source address of the specified channel
*/
extern	ULONG	Dd_PMC_HDMAC_Get_Src_Addr( UCHAR ch );

/**
set the destination address (DMACDA) of the specified channel is acquired.

@param [in] ch				Channel number (0 to 7)
@param [in] dst_addr		Destination address of the specified channel
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Set_Dst_Addr( UCHAR ch, ULONG dst_addr );

/**
The value of the destination address (DMACDA) of the specified channel is acquired.

@param [in] ch				Channel number (0 to 7)
@retval dst_addr					Destination address of the specified channel
*/
extern	ULONG	Dd_PMC_HDMAC_Get_Dst_Addr( UCHAR ch );

/**
Source Protection code is set.

@param [in] ch					Channel number (0 to 7)
@param [in] protect_code		Source Protection Code (4'b0000 to 4'b1111)<br>
								AHB HPROT[3:0] value.<br>
								[0] = 0:Opcode fetch, 1:Data access (Not effect)<br>
								[1] = 0:User mode access, 1:Supervisor mode access (Not effect)<br>
								[2] = 0:Nonbufferable access, 1:Bufferable access (Not effect)<br>
								[3] = 0:Noncachable access, 1:Cachable access<br>
@retval D_DDIM_OK					OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Set_Source_Protect( UCHAR ch, UCHAR protect_code );

/**
Destination Protection code is set.

@param [in] ch					Channel number (0 to 7)
@param [in] protect_code		Destination Protection Code (4'b0000 to 4'b1111)<br>
								AHB HPROT[3:0] value.<br>
								[0] = 0:Opcode fetch, 1:Data access (Not effect)<br>
								[1] = 0:User mode access, 1:Supervisor mode access (Not effect)<br>
								[2] = 0:Nonbufferable access, 1:Bufferable access (Not effect)<br>
								[3] = 0:Noncachable access, 1:Cachable access<br>
@retval D_DDIM_OK					OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Set_Destination_Protect( UCHAR ch, UCHAR protect_code );

/**
Arbitration mode is set.

@param [in] arbitration		Arbitration mode. (0 or 1)
@retval D_DDIM_OK					OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
@remarks There is an influence in all channels when setting it because it is a common register to all channels.
*/
extern	INT32	Dd_PMC_HDMAC_Set_Arbitration( UCHAR arbitration );

/**
Arbitration mode is read.

@param [out] *arbitration		Arbitration mode.
@retval D_DDIM_OK					OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
*/
extern	INT32	Dd_PMC_HDMAC_Get_Arbitration( UCHAR *const arbitration );

/**
Arbitration mode is returned to an initial value.

@remarks There is an influence in all channels when setting it because it is a common register to all channels.
*/
extern	VOID	Dd_PMC_HDMAC_Clear_Arbitration( VOID );

/**
The operation of All HDMAC channel is stopped.
*/
extern	VOID	Dd_PMC_HDMAC_Stop_All_Ch( VOID );

/**
The operation of All HDMAC channel is resumed.
*/
extern	VOID	Dd_PMC_HDMAC_Resume_All_Ch( VOID );

/**
It is API that returns the value set to the register of TW. 

@param [in] src_addr			soruce address
@param [in] dst_addr			destination address
@param [in] total_size			total size
@retval TW value set to register of TW
@remarks Total MAX size of this API as following.<br>
         	WORD transfer (source address and destination address are 4byte alignment) : MAX size is 4MByte.<br>
         	HALF WORD transfer (source address and destination address are 2byte alignment) : MAX size is 2MByte.<br>
         	BYTE transfer (source address and destination address are 1byte alignment) : MAX size is 1MByte.<br>
*/
extern	UCHAR	Dd_PMC_HDMAC_Get_Trns_Width( ULONG src_addr, ULONG dst_addr, ULONG total_size );

/**
Set Interrupt handler address.

@param [in] ch				Channel number (0 to 7)
@param [in] *int_handler	callback function pointer
*/
extern	VOID	Dd_PMC_HDMAC_Set_Int_Handler( UCHAR ch, VOID (*int_handler)(VOID) );

/**
Interrupt handler of HDMAC for transfer process is finished.<br>
The register value of CSTR is set to the argument of the callback function of the user registration.<br>
The type of the argument is "USHORT*" type.

@param [in] ch				Channel number (0 to 7)
*/
extern	VOID	Dd_PMC_HDMAC_Int_Handler( UCHAR ch );



#ifdef CO_DDIM_UTILITY_USE
//---------------------- utility section -------------------------------
/**
HDMAC forwarding between SDRAM-SDRAM.<br>
It doesn't wait until the forwarding completion is done. (Asynchronization)

@param [in] ch			Channel number (0 to 7)
@param [in] src_addr	source address
@param [in] dst_addr	destination address
@param [in] size		transfer size
@param [in] *intHandler	Pointer of callback function
@retval D_DDIM_OK						OK
@retval D_DD_PMC_HDMAC_INPUT_PARAM_ERR	Input Parameter Error
@retval D_DD_PMC_HDMAC_BUSY_ERR		HDMAC is being forwarded. 
@remarks The unit of forwarding makes a large size give priority.<br>
         Please call Dd_PMC_HDMAC_Open() before calling this function.<br>
         Please call Dd_PMC_HDMAC_Close() when the HDMAC forwarding ends. <br>
         <br>
         Transfer MAX size of this API as following.<br>
         	WORD transfer (source address and destination address are 4byte alignment) : MAX size is 4MByte.<br>
         	HALF WORD transfer (source address and destination address are 2byte alignment) : MAX size is 2MByte.<br>
         	BYTE transfer (source address and destination address are 1byte alignment) : MAX size is 1MByte.<br>
*/
extern	INT32	Dd_PMC_HDMAC_Copy_SDRAM_Async( UCHAR ch, ULONG src_addr, ULONG dst_addr, ULONG size, VP_CALLBACK intHandler );

//---------------------- colabo  section -------------------------------
#endif

#ifdef __cplusplus
}
#endif

/* @} */	// dd_pmc_hdmac_api group

#endif	// _DD_PMC_HDMAC_H_
